The present invention relates to CMOS circuits and, in particular, to a circuit for reducing output and ground voltage undershoot on the ground reference of a CMOS circuit.
Transient noise can be a problem in CMOS circuits having multiple switching outputs. When the output of a CMOS circuit makes a transition from a logic high state to a logic low state as illustrated by signal V.sub.OUT in FIG. 1A, any load capacitance at the output of the CMOS circuit will typically discharge through a package parasitic inductance thereby providing a current to ground as illustrated by signal I.sub.GND in FIG. 1B. It is worth noting that due to the voltage-current relationship for a capacitor, the signal I.sub.GND is the derivative of signal V.sub.OUT where it is assumed that the capacitor of interest is the load capacitor. Further, time T.sub.MAX (shown in FIG. 1) is the itme at which signal V.sub.OUT changes its point of inflection thereby resulting in a change from a positive to a negative slope for signal I.sub.GND. Further, the flow of current signal I.sub.GND over a period of time will induce unwanted positive and negative voltage spikes on the ground reference of a CMOS curcuit as illustrated by signal V.sub.GND in FIG. 1C. Similarly, due to the voltage-current relationship for an inductor, signal V.sub.GND is the derivative of signal I.sub.GND where it is assumed that the inductor of interest is the package parasitic inductor. The signals shown in FIGS. 1A-1C show the relationship between switching output signal V.sub.OUT, the output discharge current I.sub.GND and the ground voltage V.sub.GND as a function of time. Referring specifically to FIG. 1C, the positive portion of signal V.sub.GND represents the overshoot voltage or the positive ground bounce, while the negative portion of signal V.sub.GND represents the undershoot voltage or the negative ground bounce wherein both positive and negative ground bounce occur as a result of the output of the CMOS circuit making a transition from a logic high state to a logic low state. Further, it should be realized that if the slope of line segment 12 in FIG. 1B could be decreased as shown by line segment 14 in FIG. 1D, the time duration of the undershoot voltage would be increased, but the peak negative voltage of the undershoot voltage would be substantially reduced as illustrated by signal V.sub.GND in FIG. 1E. Further, the peak negative undershoot voltage is typically of greater importance than the duration of the voltage undershoot since large negative undershoot voltages can create dynamic threshold problems as is known.
In the past, at least one circuit for reducing the positive ground bounce or overshoot voltage is known. For example, U.S. Pat. No. 4,791,521, by Kenneth W. Ouyang, assigned to Western Digital Corporation and having an issue date of Dec. 13, 1988 discloses a circuit for reducing the level or transient noise for the positive slope of the ground current. However, the patent does not disclose a circuit to reduce the peak negative undershoot voltage.
Hence, a need exists for a circuit that reduces the output and ground voltage undershoot on the ground reference of a CMOS circuit.